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PIC18CXX2
DS39026C-page 120
2001 Microchip Technology Inc.
REGISTER 14-3:
SSPCON2: MSSP CONTROL REGISTER2
R/W-0
GCEN
ACKSTAT
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
bit 7
bit 0
bit 7
GCEN: General Call Enable bit (In I2C Slave mode only)
1
= Enable interrupt when a general call address (0000h) is received in the SSPSR
0
= General call address disabled
bit 6
ACKSTAT: Acknowledge Status bit (In I2C Master mode only)
In Master Transmit mode:
1
= Acknowledge was not received from slave
0
= Acknowledge was received from slave
bit 5
ACKDT: Acknowledge Data bit (In I2C Master mode only)
In Master Receive mode:
Value that will be transmitted when the user initiates an Acknowledge sequence at the end of
a receive.
1
= Not Acknowledge
0
= Acknowledge
bit 4
ACKEN: Acknowledge Sequence Enable bit (In I2C Master mode only)
In Master Receive mode:
1
= Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit.
Automatically cleared by hardware.
0
= Acknowledge sequence idle
bit 3
RCEN: Receive Enable bit (In I2C Master mode only)
1
= Enables Receive mode for I2C
0
= Receive idle
bit 2
PEN: STOP Condition Enable bit (In I2C Master mode only)
SCK Release Control:
1
= Initiate STOP condition on SDA and SCL pins. Automatically cleared by hardware.
0
= STOP condition idle
bit 1
RSEN: Repeated START Condition Enabled bit (In I2C Master mode only)
1
= Initiate Repeated START condition on SDA and SCL pins.
Automatically cleared by hardware.
0
= Repeated START condition idle
bit 0
SEN: START Condition Enabled bit (In I2C Master mode only)
1
= Initiate START condition on SDA and SCL pins. Automatically cleared by hardware.
0
= START condition idle
Note:
For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode,
this bit may not be set (no spooling) and the SSPBUF may not be written (or writes
to the SSPBUF are disabled).
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR reset
’1’ = Bit is set
’0’ = Bit is cleared
x = Bit is unknown
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